Senior Staff Physical Design Engineer – Contractor/Freelance (FinFET Specialist)

About Us

Vertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architecture. Our mission is to redefine the well-known trade-offs of semiconductor memory devices, ultimately enabling the future of computing.

We are welcoming passionate, experienced, and forward-thinking colleagues to join our dynamic team and disrupt the industry together.

About What You Will Do

As a Senior Staff Physical Design Engineer, you will take technical leadership in the physical implementation of next-generation high-performance SoCs targeting 16nm FinFET technologies and below.

In this role, you will:

• Lead the full RTL-to-GDSII physical implementation flow, including synthesis, floorplanning, place & route, CTS, timing closure, and sign-off.

• Define and execute implementation strategies optimized for FinFET technologies, addressing challenges such as secondary power grids, track patterns, and advanced DRC constraints.

• Perform Multi-Mode Multi-Corner (MMMC) timing closure and power optimization to achieve the best PPA (Power, Performance, Area) targets.

• Conduct power integrity analysis and ensure robust IR drop and electromigration (EM) margins.

• Drive physical verification closure including DRC, LVS, ERC, and antenna checks using industry-standard sign-off tools.

• Collaborate closely with RTL and DFT teams to ensure physically aware synthesis, efficient scan-chain integration, and congestion mitigation.

• Interface with foundries and EDA vendors to address technology-specific implementation challenges.

• Contribute to EDA flow improvements and automation through scripting (Tcl, Python, or Perl) to enhance productivity and design quality.

• Act as a technical pillar and mentor within the physical design team, supporting complex debugging and advanced optimization strategies.